This invention relates to circuits and techniques for generating clock signals which have predetermined temporal relationships with reference signals. More specifically, this invention relates to clock alignment circuits and techniques, for use in high speed integrated circuit devices, which generate clock signals having a synchronous, precisely controlled, and/or predetermined relationship with reference signals and which exhibit wide operating ranges in clock alignment, reduced power dissipation, increased power supply noise immunity, and decreased process and temperature variation sensitivity.
Clock alignment circuits are required in many of today's high speed integrated circuit devices to generate a clock signal having a certain timing relationship with a reference signal. In short, clock alignment circuits are employed to generate clock signals having a synchronous, precisely controlled, and/or predetermined relationship with a reference signal (e.g., an external clock signal). By integrating clock alignment circuitry into a clock system of, for example, a microprocessor or synchronous memory device, difficulties relating to maintaining or ensuring signal integrity and clock skew may be overcome. In addition, reliable clocking operations which support very high speed circuit implementations may be achieved.
Examples of clock alignment circuits and techniques include phase lock loop (PLL), and delay lock loop (DLL) circuits among many others. A PLL circuit, for example, utilizes a voltage controlled oscillator (VCO) to generate a recovered clock signal having a certain timing relationship with the reference signal. Similarly, a DLL may employ a voltage controlled delay line (VCDL) to generate the recovered clock signal. Both of these types of clock alignment circuits involve techniques which detect a phase or delay error between the internal clock signal and the external clock signal (reference signal) and provide a feedback loop to compensate for the phase or delay error between the signals.
A shortcoming of some conventional clock alignment circuitry and techniques is the ability to consistently address power supply noise generated by large switching circuits (e.g., output drivers). Large currents and fast switching of these circuits tend to induce noise on power supply systems. The power supply systems, in addition to providing power to the switching circuits, also supply power to clock circuitry located on the same integrated circuit substrate. Noisy power supplies tend to distort or skew a clock signal generated in, for example, a delay element in a DLL or PLL system. Power supply noise may also introduce variations between clock cycles of internal clock signals used in the clock alignment system on an integrated circuit device.
Furthermore, substrate or ground induced noise, variations in semiconductor processing, and changing temperatures may also cause distortions in clock signals. Noise sources and environmental effects may impose a serious limitation to the performance of clock alignment circuit designs.
A schematic block diagram of a conventional clock alignment system based on a DLL approach is shown in FIG. 1. DLL clock alignment system 1 includes a reference clock 16 and an output clock 15 each inputting into a phase comparator 11. The output clock 15 represents an internally compensated (i.e. delayed clock) or recovered clock which is to be “locked” by a delay relationship to the reference clock 16 (i.e. input clock). The phase comparator 11 detects any relative phase misalignment between the reference clock and the output clock 15 and generates an UP output 17 and a DN output 18 to indicate a relatively early or late phase misalignment (i.e., phase error). The outputs 17 and 18 are then applied to a charge pump circuit 12 which integrates the UP and DN outputs 17 and 18 into a charge pump voltage (Vcp) on output line 19.
A bias generator circuit 13 receives the charge pump voltage (VCP) and generates a PMOS transistor bias voltage (VBP) on output line 20, and an NMOS transistor bias voltage (VBN) on output line 21. Both VBP and VBN scale relative to VCP to bias delay elements in a voltage controlled delay line (VCDL) 14. The VCDL 14 will delay the reference clock 16 by a fixed amount which is defined by the phase error to form the output clock 15 such that there is negligible or no detected phase error between the reference clock 16 and the output clock 15.
Here, the output clock 15 is immune from power supply noise since any skew in the output clock 15 resulting from a power supply fluctuation is detected and corrected by tracking the delay through the VCDL 14. The delay through the VCDL 14 is tracked in accordance to the integrated phase error resulting from any skew caused by the power supply fluctuation.
A schematic block diagram of a conventional clock alignment system using a PLL approach is shown in FIG. 2. The structure and operation of PLL clock alignment system 2 is similar to the structure and operation of DLL clock alignment system 1 illustrated in FIG. 1. In the PLL clock alignment system 2, however, a VCO is employed in place of a VCDL. Briefly, with reference to FIG. 2, a reference clock 26 and an output clock 25 are input into a phase comparator which generates a phase error information in the form of UP output 27 and a DN output 28. A charge pump circuit 22 integrates the UP and DN outputs 27 and 28 into a charge pump voltage 29. A bias generator 23 generates a PMOS transistor bias voltage (VBP) on output line 30 and an NMOS transistor bias voltage (VBN) on output line 31. Both VBN and VBP scale with VCP to bias delay elements in a VCO 24. The negative feedback in the loop adjusts the VCO output frequency by integrating the phase error that results between the reference clock 26 and the output clock 25. As in the DLL clock alignment system 1 of FIG. 1, output clock 25 in FIG. 2 tends to be immune from power supply noise since any skew in the output clock 15 resulting from power supply fluctuations is detected and corrected by tracking the skew through the VCO 24.
Conventional DLL and PLL circuits attempt to minimize susceptibility to noise by using delay elements which have low sensitivity to power supply noise. The delay elements used in the conventional VCDL and the VCO of FIGS. 1 and 2 attempt to accomplish this by employing a differential buffer delay stage. With reference to FIG. 3, a conventional differential buffer delay stage 300 includes a symmetric source coupled pair of input transistors 301 and 302, each coupled in series with symmetric load elements. Each symmetric load element includes a diode connected PMOS device 305 connected in shunt with an equally sized PMOS device 304. Each of the PMOS load device 304 is biased by the PMOS transistor bias voltage (VBP) generated in FIGS. 1 and 2. Similarly, an NMOS pulldown bias transistor 307 is biased by the NMOS transistor bias voltage (VBN) generated in FIGS. 1 and 2. These transistor bias voltages VBP and VBN, are continuously adjusted to provide a correct current flowing through the delay stage 300 independent of supply voltage. If the supply voltage changes, VBP and VBN will compensate to keep a constant current flowing through the delay stage 300.
The conventional techniques and circuitry described above often allow for a very broad frequency range of operation. In addition, the conventional techniques provide some immunity from adverse effects based on the process technology of the integrated circuit and environmental conditions as well as power supply fluctuations. However, conventional differential amplifier type delay elements tend to consume high levels of static power. As such, these delay elements are undesirable or not compatible for use in many applications—for example applications which require low power dissipation, such as, portable battery operated applications. Indeed, the differential amplifier type delay elements of FIG. 3 dissipates more static power than typical static inverter type elements. Static inverter elements, while having negligible static power dissipation, tend to be much more susceptible to power supply fluctuations than differential amplifier type delay elements.
Thus, conventional clock alignment circuit employing differential elements in a delay line may provide the advantage of high noise immunity but tend to suffer from unacceptable power consumption levels. Employing static inverter elements in the delay line as a substitute for differential elements may solve concerns relating to power consumption but may also introduce a considerably lower noise immunity than differential delay elements.
In an effort to overcome the lower noise immunity concerns presented by static inverter elements, conventional clock alignment circuits have employed regulated power supplies to power inverter type delay elements. One such regulated power supply which offers some relief to lower noise immunity of the inverter type delay line elements is illustrated in FIG. 4. With reference to FIG. 4, a band gap voltage regulator 400 provides a power supply to inverter type delay line elements (not shown). Here, the band gap voltage regulator 400 includes an internal band gap voltage reference generator 401 which generates a reference voltage (VREF). The reference voltage VREF is applied to a regulator 402 to generate an internal supply voltage at an output node 403. The internal supply voltage powers the inverter type delay elements in the delay line. The internal band gap voltage reference generator 401 is regulated from any power supply noise or fluctuations and provides a stable voltage since it is based on a physical constant of silicon.
There are a number of drawbacks in using the regulated power supply approach to improve immunity from power supply noise. For example, implementing the band gap regulator 400 may require special analog circuit design techniques. In addition, the band gap regulator 400 may consume unacceptable levels of power at low clock alignment system operating frequencies. Moreover, a portion of the clock alignment circuitry may have to operate at a lower supply voltage, thereby adding additional design complexity. Thus, although the noise susceptibility of the static inverter element may be improved through the use of the band gap regulator 400, the improvement is realized at the cost of increased complexity and power consumption.
As an alternative, conventional clock alignment circuits have employed a dedicated pin to provide a “quite” power supply. By providing a dedicated pin to supply power to delay line elements, much of the complexity involved with the band gap regulator 400 may be avoided. In addition, by employing static inverter type delay elements, significant noise immunity may be realized along with negligible static power consumption penalty. However, the dedicated pin approach may require additional area on an integrated circuit for the inclusion of an extra bond pad. In addition, the dedicated pin approach may have limited applications. For example, applications where additional pins do not significantly impact the feasibility of a design. Also, the dedicated pin approach may render the clock alignment circuitry susceptible to other sources of noise such as ground induced noise or substrate coupled noise.
Thus, in sum, although clock alignment circuits employing differential delay elements provide a relatively high noise immunity, such circuits suffer from unacceptable power consumption levels. Static inverter elements employed in the delay line may have lower power consumption (relative to differential delay elements) but have the disadvantage of lower noise immunity. Although noise susceptibility of the static inverter element may be improved through the use of regulated power supplies, such as a bandgap regulator, such a configuration may also impose undesirable complexity and consume excess power. A dedicated power supply pin may solve the noise susceptibility concerns of the static inverter element, however dedicated pin designs tend to impose additional integrated circuit area requirements and may have limited applications.
Accordingly, there is a need for clock alignment circuits which overcome the shortcomings of conventional circuitry for use in high speed integrated circuit devices to generate the output clock having a predetermined or synchronous timing relationship with the reference signal. In addition, there exists a need for circuits and techniques to minimize effects due to process and temperature variations which notably overcome disadvantages of conventional clock alignment circuitry. There is a need for an approach which offers lower relative power consumption advantages while having high immunity to noise sources.
The static inverter delay line element approach may offer inherent static power consumption but may otherwise exhibit poor noise susceptibility. The regulated supply approach while providing increased noise immunity to the static inverter delay line element, may require undesirable complexity and exhibit unscalable power consumption. Thus, there is also a need for a regulator circuit which introduces a minimal amount of additional complexity and may be included in a clock alignment circuit. There is a need for such a regulator circuit to achieve power dissipation which scales with operating frequency and process speed. In this regard, as operating frequency decreases, the delay element will consume less power in scaled proportion. Moreover, there is a need for a circuit and technique which may be ported to a process which supports faster circuit operation while consuming less power.